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Overview
This workshop discusses at-speed faults and how to use TetraMAX for at-speed test. Topics include description, recommendation, and scripts of transition, small-delay defect, and path-delay fault model ATPG. Also covered are the Onchip Clock Controller (OCC) flow, which leverages the PLL fast clocks, and using PrimeTime to generate the necessary data for at-speed test. Hands-on labs follow each training module, allowing you to apply the skills learned in lecture. Labs include: using PrimeTime to generate the necessary files for at-speed ATPG; generating the patterns for different fault models in Tetramax; and, finally, using VCS for simulating the patterns generated. Objectives At the end of this workshop the student should be able to:

Describe the need for At-Speed testing
List the At-Speed fault models available
Describe the two launch techniques for at-speed faults
Successfully edit a stuck-at SPF file to suit at-speed fault model
Define the timing exceptions
Automate the process of script generation for TetraMAX, using PrimeTime. This script will take care of the false and multi-cycle paths
Modify a given stuck-at fault model script to run for an at-speed fault model
State the steps required to merge transition and stuck-at fault patterns to reduce the overall patterns
Automatically create scripts that can be used in PrimeTime to perform test mode STA
Describe the SDD flow
Describe the flow needed to successfully use the PLL present in your design to give the at-speed clock during capture mode
State the steps needed to perform path-delay ATPG
Understand the fault classification in path-delay ATPG

Audience Profile
Engineers who use ATPG tools to generate patterns for different fault models.Prerequisites
To benefit the most from the material presented in this workshop, you should: A. Have taken the TetraMAX 1 workshop. OR B. Possess knowledge in the following areas:

Scan Architecture and ATPG
Stuck-At fault model ATPG with TetraMAX
SPF file

Course Outline Module 1

Introduction of At-Speed defects
Source of Test Escapes and chip failure
Requirements for At-Speed testing
Popular fault models for At-Speed testing

Module 2

Transition Fault model
Path Delay Fault model
At-Speed Fault Detection Method
Techniques to Launch and Capture a Fault

Module 3

STIL file
Modifications to STIL file for At-Speed testing
Generic Capture Procedures

Module 4

Timing Exceptions
Automated Way to Generate Timing Exceptions form PrimeTime

Module 5

TetraMAX Scripts for Transition ATPG
Design Guidelines
Flow Considerations and Requirements
Pattern Merging
Automated way to generate the scripts for PrimeTime to perform testmode STA

Module 6

What is a Small Delay Defect ATPG
How to use PrimeTime to Generate the Slack Data
ATPG Flow in TetraMAX

Module 7

Requirement of PLL for At-speed faults
The various clocks in PLL flow
Use QuickSTIL to generate the SPF

Module 8

TetraMAX scripts for Path Delay ATPG
Fault Classification for Path Delay Faults
Generating Paths for TetraMAX Using PrimeTime
Reconvergence Paths
Hazard Simulation

Module 9

Conclusion
Topics Covered
Fault model and Features of TetraMAX
Solvnet Resources

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